[Oberon] RISC5

Jörg joerg.straube at iaeth.ch
Tue Apr 15 15:26:43 CEST 2014

Hi Paul

Depends on the definition of "emulated" vs "implemented" :-)

Couldn't you do the following analogy?
 Verliog code  = PdWs emulator code
 Verilog tools = C compiler
 Spartan 3     = host environment


-----Original Message-----
From: Paul Reed [mailto:paulreed at paddedcell.com] 
Sent: Dienstag, 15. April 2014 15:10
To: ETH Oberon and related systems
Subject: Re: [Oberon] RISC5

Dear Joerg,

> By definition, Project Oberon works on the imaginary RISCv5.
> NW emulated his RISCv5 on an FPGA HW
> PdW emulated the RISCv5 in C and SDL on arbiträry HW
> Short: Project Oberon is ALWAYS emulated as there is no real RISCv5 HW.

That's rubbish.  The RISC5 is implemented in hardware.


Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
-------------- next part --------------
A non-text attachment was scrubbed...
Name: smime.p7s
Type: application/x-pkcs7-signature
Size: 6097 bytes
Desc: not available
Url : https://lists.inf.ethz.ch/pipermail/oberon/attachments/20140415/90606660/attachment.bin 

More information about the Oberon mailing list