[Oberon] RISC5

Chris Burrows chris at cfbsoftware.com
Sun Apr 27 09:00:28 CEST 2014

> -----Original Message-----
> From: eas lab [mailto:lab.eas at gmail.com]
> Sent: Sunday, 27 April 2014 2:42 PM
> To: chris at cfbsoftware.com; ETH Oberon and related systems
> Subject: Re: [Oberon] RISC5
> What about a P-code interpreter for rPi? Instead of going via C:
> it's so small, it can be assembled directly. [My first pCode VM:
> Fairchild-F8 needed hex-byte-codeing!].

Most of the legwork has already been done. Read the Compiler Construction document I recently recommended to you:


Described in the book, and also at that website, you will find source code of an interpreter of the RISC instructions. The source code file is called RISC.mod and in this case it is written in Oberon. It processes most of the RISC instructions and consists of just 76 lines of code. If you have an urge to write it in assembler you could get a head start by first compiling the source in Oberon and then disassembling it and then cleanup the resulting assembly code. 

> But having Oberon, without the ETHO-interface is of little value?

On the contrary, Oberon-07 is great value for developing predictable, realtime, embedded software without an OS and without having to use C. One of the key features of the FPGA RISC instruction set is that the majority of instructions execute in a single clock-cycle on the FPGA hardware which gives you the timing predictability. 

However, those attributes are much harder to achieve when you use an emulator / interpreter rather than executing directly on the hardware. 

The other disadvantage of applications running under an interpreter is that they typically run at only about 10% of the execution speed of native-code executables. Admittedly that is not such an issue on the Raspberry Pi, which runs at a clock speed of 700MHz, if you are not worried about power consumption. 


Chris Burrows
CFB Software


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