[Oberon] Large Displays / 64 bit...

Jack Johnson knapjack at gmail.com
Fri Jun 20 20:59:13 CEST 2014

On Fri, Jun 20, 2014 at 7:30 AM, Jörg <joerg.straube at iaeth.ch> wrote:
> Just a remark to see what complexity Markus is aiming at:
> - To synthesize the whole RISC5 architecture with the CPU and all
>   input/output routines into FPGA on the SPARTAN-3 board, we have
>   today a Verilog code of approx 700 lines in total.
> - I could imagine that on the SPARTAN-6 only the driver for the SDRAM
>   alone will need approx 700 lines of Verilog code :-)

I asked about this a bit earlier. I only vaguely understand the
challenge, but the scope and impact seems to be clear in terms of the
loss of simplicity.

My question is, is this the future? If every future implementation is
going to have to tackle the SDRAM problem, it seems like there's an
opportunity there to revisit the SDRAM management/implementation
strategies and maybe find an alternate implementation that will help
continue to provide some sanity for the future.

My instinct says there are a handful of ways everyone does SDRAM, but
there may have been approaches from decades past that are worth
revisiting (or fresh approaches that are worth discovering).

Somewhere out there, some FORTH programmer has a DVD player that's brilliant. ;)


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