[Oberon] Project Oberon RISC5 Verilog
chris at cfbsoftware.com
Sat Jun 21 01:09:52 CEST 2014
> -----Original Message-----
> From: Jörg [mailto:joerg.straube at iaeth.ch]
> Sent: Saturday, 21 June 2014 1:00 AM
> To: greim at schleibinger.com
> Cc: 'ETH Oberon and related systems'
> Subject: Re: [Oberon] Large Displays / 64 bit...
> Thanks for the effort you are doing.
> Just a remark to see what complexity Markus is aiming at:
> - To synthesize the whole RISC5 architecture with the CPU and all
> input/output routines into FPGA on the SPARTAN-3 board, we have
> today a Verilog code of approx 700 lines in total.
> - I could imagine that on the SPARTAN-6 only the driver for the SDRAM
> alone will need approx 700 lines of Verilog code :-)
For those like myself who wish to comprehend this discussion and want to
experiment with the RISC5 Verilog implementation or just want to understand
how it works, I thoroughly recoomend the book:
"FPGA Prototyping by Verilog Examples" Xilinx Spartan-3 Version by Pong P.
Chu. ISBN 978-0-470-18532-2.
It starts with the very basics - Chapter 1 is titled "Gate-Level
Combinational Circuit". I'm up to Chapter 3 so far (arithmetic and shift
register operations) so it will be a while before I get to "External SRAM
controllers" which are explained in Chapter 11 ;-)
For me it is an exciting whole new world of discovery,
More information about the Oberon