[Oberon] Oberon System on the ?
felix.friedrich at inf.ethz.ch
Tue Nov 4 11:48:58 CET 2014
Dear Wojtek, all,
yes, I am reading the mailing list and in particular the discussions
around FPGA / Oberon.
From 2009 - 2013 we have worked on a Microsoft funded project called
"Supercomputer in the Pocket". Initial goal was basically educational:
develop a programming language / programming model together with a
suitable component on an FPGA to ease parallel or concurrent computing.
In the course of the project it shifted towards (medical)
high-performance applications on FPGAs. The work is ongoing and is in
the process of getting mature.
And we have reached the goal to run high-performance applications on an
FPGA. In order to achieve this, our programming model (called "Active
Cells") foresees on the one hand little general purpose cores (TRMs -
Tiny Register Machines) and on the other hand specialized computation
engines. Most important feature is that we provide access to the FPGA
from a dialect of Oberon consequently in high-level.
We have A2 (programmed in Active Oberon) running on the Zynq ARM cores
interacting with a Active Cells System on Chip on the FPGA fabric. We
have various student projects on that and other hardware and teach the
students how to go along this road in our System Construction Course.
A company has developed two products on the base of this programming
model and is successfully making business with it. Which does, by the
way, not imply that the development and toolchain is closed. Everything
implemented at ETH will be available open source.
We are in the process of writing a good introduction to the programming
model, the toolchain etc. I will post on this list when and where we
make it available.
> thank you for the reference to the Feb/2014 post by Dr. Josef Sedlacek. It
> reads very promising:
> "In collaboration with the group of prof. Jürg Gutknecht with Dr. Felix
> Friedrich and Florian Negele we have developed a system which carries
> the registered mark..."
> Dr. Felix Friedrich is a moderator of this mailing list. Is he reading
> this discussion? If they have something to offer then perhaps they could
> tell. The silence is suggestive of saying "no".
> Also let me reiterate that my own interest is in a small but efficient
> embedded system. It boils down to a question "what comes first, a horse or
> a carriage"? Basically, the FPGA-based design can be centered around
> either the Programmable Logic (PL), or a Processing System (PS). These
> terms are illustrated with the Zynq providing the dual-core hard silicon
> ARM (PS) and the attached FPGA to implement the PL part. Zynq chip can be
> used to run the Oberon System if it could be compiled for the embedded ARM
> cores. (Any volunters to port the compiler?) Lacking the compiler for the
> Zynq-ARM, one can do the same trick on a smaller scale using embedded
> RISC5, or perhaps MIPS, or whatever.
> I am interested in a pretty minimal system to run the PS in an otherwise
> PL-dominant design. In principle, the present Wirth system is OK. But it
> would help if the V4/S3 legacy could be immediately used, because it is
> simply a great and highly useful legacy. So I am asking all these
> questions hoping that someone will see the point.
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
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