[Oberon] Fwd: Re: FPGA - RISC multiply/divide

Tomas Kral thomas.kral at email.cz
Mon May 29 14:45:45 CEST 2017

On Sun, 28 May 2017 20:04:21 +0000
"Skulski, Wojciech" <skulski at pas.rochester.edu> wrote:

> In practise,  one clock for setting up values, results can be read
> one clock after calculus done; so, divide a 32 bit number use 34
> clocks. Waveforms correspond to our own VHDL version of RISC-5.

I see 34 clocks, so `DIV' is the lengthiest RISC instruction, so it

Tomas Kral <thomas.kral at email.cz>

More information about the Oberon mailing list