[Oberon] Fwd: Re: FPGA - RISC multiply/divide

Skulski, Wojciech skulski at pas.rochester.edu
Mon May 29 17:32:45 CEST 2017


not only is DIV the longest instruction, but also its timing depends on the arguments. I think that the DIV hardware should be treated like a peripheral rather than a genuine part of RISC5 CPU. Working with such a peripheral, you write the operands to the memory registers, and a while later you read the result from another register. Note that the DSP slice, which is now a standard part of any newer CPU, is capable of more than just DIV. Have a look at Spartan-6 DSP48A1 Slice Description, User Guide UG389. These beasts are highly configurable. Even more important, their features keep evolving. The Spartan-3 multiplier, which was capable of basically one thing, has now evolved into a complicated coprocessor capable of many other things. IMHO, trying to catch up with all these capabilities by adding them to the language is going to fail, because it is a moving target, which depends on the FPGA generation and the FPGA vendor. IMHO, a safer approach is to move the advanced numerics away from the language proper into the application domain.

This leaves us with a question what to do with DIV. Is it appropriate to define DIV in the language and implement it with fabric logic without using the DSP slices? One can let DIV become a part of the official RISC5, if it is not done already. In such a way the problem is solved at the lowest denominator level, while advanced numerical applications can use DSP slices as peripherals.


From: Oberon [oberon-bounces at lists.inf.ethz.ch] on behalf of Tomas Kral [thomas.kral at email.cz]
Sent: Monday, May 29, 2017 8:45 AM
To: oberon at lists.inf.ethz.ch
Subject: Re: [Oberon] Fwd: Re:  FPGA - RISC multiply/divide

On Sun, 28 May 2017 20:04:21 +0000
"Skulski, Wojciech" <skulski at pas.rochester.edu> wrote:

> In practise,  one clock for setting up values, results can be read
> one clock after calculus done; so, divide a 32 bit number use 34
> clocks. Waveforms correspond to our own VHDL version of RISC-5.

I see 34 clocks, so `DIV' is the lengthiest RISC instruction, so it

Tomas Kral <thomas.kral at email.cz>
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