[Oberon] RISC-5 and memory

Skulski, Wojciech skulski at pas.rochester.edu
Fri Oct 6 19:53:00 CEST 2017

From: Oberon [oberon-bounces at lists.inf.ethz.ch] on behalf of peter at easthope.ca [peter at easthope.ca]

> How many MiB would you want?

Enough for V4, S3, and Component Pascal running natively on RISC5. I would guess 16 MB should be enough, but more is better.

I am not sure if anyone will implement CP on RISC5, but having more RAM will make it possible in principle. Now it is hardly possible even in a dreamland.

> Naive question: is modification of an exiting board
> to add SRAM on an auxiliary board possible?

Magnus can make Pepino with 2MB. Pipistrello has 64 MB, but it does not run Oberon. Running Oberon on Pipistrello should be possible after merging the Oberon HDL with the memory interface. Pipistrello has the HDMI output, though it needs to run through the HDMI core. So here is another core to be interfaced.

> Oberon can't be the only interest wanting more SRAM.  Given the human
> tendency of always wanting bigger and more, commercial boards with 4,
> 8, 16 ... MB SRAM can't be to far over the horizon.

Arty has 256 MB of DDR3 running at 667 megabits/s/pin, but it does not offer a monitor output. Arty is not an ideal platform. Pipistrello has enough RAM and it has color output, but it will require advanced HDL programming.

I am working on a board with an easy color output and 256 MB of DDR3. It will eventually get done one day.


More information about the Oberon mailing list