[Oberon] FPGA - Colour Support
joerg.straube at iaeth.ch
Sun Oct 8 17:55:09 CEST 2017
Magnus Verilog code for color does not allow to have a separate B/W screen.
His code assumes that 4 consecutive bits in memory form one color pixel.
Other memory organization are thinkable. Eg stacked 1bit planes. With such an memory organisation it would be easy to increase the bits per pixel from 1,2,3 and so on. If you clear the whole framebuffer and only write to the first plane, you have B/W.
But the BIG drawback of such a color memory scheme is, that every color pixel needs several memory accesses, one per plane.
I thnk consecutive pixels are more efficient. Generalizing Display.Mod from 1 to 2,4 or 8 bpp is a good exercise.
> Am 08.10.2017 um 16:06 schrieb Tomas Kral <thomas.kral at email.cz>:
> Hi Joerg, Wojtek, Magnus, All,
> Thanks for all your posts and recommendations.
> - 2MB of RAM, something I plan by chip piggy back, while driving upper
> meg with CS, from `Verilog' code.
> - overclock to 30MHz
> As I have got `Pepino' board with 1MB, and 25Mhz, this can make an
> interesting exercise for students.
> What I need to solve however first, is how to map b&w screen
> in memory completely separate from colour bit planes. This would allow
> using `Display.Mod' unchanged while programming colour logic.
> In other words, one bit in memory tells if the display pixel is
> illuminated or not, the other bit planes, tell if there are also some
> colours to add to it.
> In the two designs I have got so far, several bits in memory control RGB
> of a single display pixel, this results in seeing entire display buffer
> duplicated several times on the monitor.
> Tomas Kral <thomas.kral at email.cz>
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
More information about the Oberon