[Oberon] FPGA Design basic
waltergallegos at vera.com.uy
Mon Oct 9 01:59:21 CEST 2017
¿ Do you know what "synchronous design" means in FPGA?
Never never generate a clock with logic, this is first rule that I
declare in my trainings.
For who are not formed in FPGA, a clock generated with logic are -
asynchronous - and out of your control.
Please do not use HDL sentences to generate clock signals, FPGA is not software is hardware.
More information about the Oberon