[Oberon] FPGA Design basic

[Jörg]

Walter

I didn't program any FPGA myself. I was just studying the Verilog source code that comes with ProjetOberon.
I learned now, that this code does seem to follow best practices.

I don't want to defend somebody elses code, I only wonder what consequence it has as the generated signals "clk0" and "pixclk" are only used once. There are not several blocks that have to be clocked synchronous.

br
Jörg

-----Original Message-----
From: Oberon [mailto:oberon-bounces at lists.inf.ethz.ch] On Behalf Of Walter Gallegos
Sent: Monday, October 09, 2017 1:59 AM
To: ETH Oberon and related systems <oberon at lists.inf.ethz.ch>
Subject: Re: [Oberon] FPGA Design basic

Jörg,

¿ Do you know what  "synchronous design" means in FPGA?

Never never generate a clock with logic, this is first rule that I
declare in my trainings.

For who are not formed in FPGA, a clock generated with logic are -
asynchronous - and out of your control.

Please do not use HDL sentences to generate clock signals, FPGA is not software is hardware.

Walter


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