[Oberon] FPGA - Accessing DRAM
chris at cfbsoftware.com
Mon Oct 16 13:02:42 CEST 2017
> -----Original Message-----
> From: Oberon [mailto:oberon-bounces at lists.inf.ethz.ch] On Behalf Of
> Paul Reed
> Sent: Monday, 16 October 2017 6:53 PM
> To: ETH Oberon and related systems
> Subject: Re: [Oberon] FPGA - Colour Support
> Having said all that, one way the early micros simplified their
> dynamic RAM interface is by realising that due to the row/column
> nature of DRAM, they could dispense with hardware refresh, if all the
> rows could be guaranteed to be accessed within the refresh period.
Coincidentally, I've just implemented a 4164 DRAM chip tester using
Oberon-07 and a $13 Nucleo STM-32 development board that does just that.
Oberon-07 with its SET type, bit manipulation capabilities and predictable
instruction execution times, made the task really simple.
It was one of those spin-off projects that takes on a life of its own. The
primary project was to restore a 1983 Sage II 68000 computer which only
recognised 256K of the 512K DRAM installed - 72 chips in all! The DRAM
tester only takes a few seconds to test each chip so I was able to identify
and replace the faulty chips in one session.
Some ZIF sockets and Veroboard arrived today which I'm planning to use to
publish as a basic example Oberon-07 construction project in the very near
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