[Oberon] Arduino MKR Vidor 4000 (was New Hardware for Oberon / Risc-5 ?)
joerg.straube at iaeth.ch
Fri Jul 27 09:21:40 CEST 2018
Simple porting of the RISC-5 willl be difficult to that board as this CPU does not support a cache. First as Wojtek correctly pointed out, it‘s SDRAM, but secondly the AS4C4M16SA-7BCN is organized as 16x 4Mb.
Good, let’s assume the RISC-5 would evolve to RISC-6 adding an instruction and a data cache to overcome the longer SDRAM start time until full transfer speed is reached, this cache has to be used as well to make it look like a 32 bit architecture.
> Am 27.07.2018 um 03:43 schrieb Skulski, Wojciech <skulski at pas.rochester.edu>:
> Markus wrote:
>> Arduinio brought a brand new FPGA board to the market!
>> Its quite cheap (50 EUR) and seems to have 8 MByte of SRAM
> The website says "onboard 8 Mbyte SDRAM". SDRAM is not SRAM. It is hard to say for sure what they installed because neither the schematic nor the BOM are prominently displayed on that website. Maybe they are there somewhere. But I assume they know what they are saying.
> I cancelled my previous Oberon board project after realizing the intricacies of caching. I do not want to say that SDRAM is bad. But I decided to shy away from it. Another concern is indeterministic software execution time, depending on the cache status and thus on execution history. This would be bad for my field of study.
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