[Oberon] Moving oberon to RISCV?

Paul Reed paulreed at paddedcell.com
Fri Jul 27 13:16:01 CEST 2018

Hi Joerg,

> the myriads of processors out there, the idea was: keep the compiler
> constant and make it generate code for „his“ RISC-5 processor. By using
> FPGA, you then „only“ have to implement this processor on a chosen FPGA
> platform.

No, there was no such idea here, simply the opportunity of being able to
design an ideal processor architecture for the problem at hand.

See his 80th birthday symposium talk, the last talk at


I think it's important to bear in mind that for Prof. Wirth the FPGA is
simply a means to a particular end.


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