[Oberon] Moving oberon to RISCV?

Jörg joerg.straube at iaeth.ch
Fri Jul 27 12:43:46 CEST 2018

If you mean this RISCV (https://en.m.wikipedia.org/wiki/RISC-V), then you need to change the code generator of the oberon compiler to generate RISCV instructions.

In my point, this is exactly the opposite of what Wirth wanted to reach with RISC-5. In his career he ported his compiler to quite some processors. But instead of porting the compiler over and over again to the myriads of processors out there, the idea was: keep the compiler constant and make it generate code for „his“ RISC-5 processor. By using FPGA, you then „only“ have to implement this processor on a chosen FPGA platform.


> Am 27.07.2018 um 12:09 schrieb Travis Ayres <trayres at gmail.com>:
> I realize this is a lot of work, but there's quite a bit of momentum for RISCV. What would need to be done to port Oberon?
> --
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
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