[Oberon] NAstrobe for RISC5 on Pepino

Skulski, Wojciech skulski at pas.rochester.edu
Tue Jul 31 15:37:56 CEST 2018


  may I update the subject to better fit the content?

> We have just finished preparing a new disk image and Verilog bitstream files 
> specifically to run the Project Oberon Workstation on the Pepino LX9 FPGA 
> development board 'out-of-the-box'.

This is great. We have this board.

> This release is based on the very latest Oberon sources (July 2018) and Verilog sources
> (Jun 2018) as described in 'An Update of the RISC5 Implementation', by Niklaus Wirth 15.6.2018:

> The system also includes our enhancements: Support for Numeric / Character CASE statements 
> in the compiler, optional real-time clock devices, timestamps on uploaded files, the additional 
> high-capacity file system HCFiler and more source code examples. The entire source code of the system, 
> including the compiler, is included on the disk image. 

Wonderful. You are aware that the compiler has been very recently merged with Experimental Oberon? 
Is yours the same as the latest official compiler?

I looked at the NW document. There is a statement there "memory access requires two clock cycles, 
and the processor must be stalled for one cycle". It is puzzling in the context of the ZBT RAM, 
where every access requires two clock cycles. I wonder if these two facts can somehow 
be merged to increase the effective processor speed when the main RAM is ZBT. 

It is just an idea which I have not explored yet.

Thank you for this piece of work. It is wonderful.


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