[Oberon] LDPSR

Chris Burrows chris at cfbsoftware.com
Sat Oct 13 02:07:09 CEST 2018

> -----Original Message-----
> From: Oberon [mailto:oberon-bounces at lists.inf.ethz.ch] On Behalf Of
> Skulski, Wojciech
> Sent: Saturday, 13 October 2018 12:47 AM
> To: ETH Oberon and related systems
> Subject: Re: [Oberon] LDPSR
> Chris:
>   OK, I stand corrected. The details should be in the implementation
> notes. OK, are these available for the RISC5 Oberon System? 

Yes - you just need to know where to find them. 

The use of LDPSR in association with interrupts is described with an example
in the recent update to the project Oberon documentation:

  An Update of the RISC5 Implementation Niklaus Wirth, 15.6.2018

"This note describes an update of the implementation of the RISC5 processor,
described in Verilog and
implemented on an FPGA.:

The file is called RISC5Update.pdf and it can be downloaded from:



Chris Burrows
CFB Software

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