[Oberon] Bit manipulation in Oberon-07

Peter Matthias PeterMatthias at web.de
Sat Oct 27 21:23:47 CEST 2018

Am 27.10.18 um 19:53 schrieb Jörg Straube:
> Luckily in this case the bit numbering of Cortex M and the bit numbering of RISC5 are identical, both use LSB0. But if one CPU used MSB0 and the other LSB0, what is the definition of the UBFX arguments then?

Are there still architectures available that use MSB0? Even if, the 
compiler can define MSB0.

> UBFX(7,3) can be written as „DIV 128 MOD 8“

... which the ARM compiler easily can fuse to one UBFX instruction.


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