[Oberon] Oberon 2 compiler for RISC5

Jörg joerg.straube at iaeth.ch
Thu Nov 8 20:01:05 CET 2018


Worth mentioning: Ceres had 256 kB video RAM, ADDITIONAL to the 2 MB RAM.
The 256 kB where used to host TWO bitmaps of 1024 x 800 monochrome pixels.
Bitmaps could be displayed alternatively.
While drawing with Display.Mod: y value 0..799 were one bitmap, y values
-800..-1 were the other bitmap.

This is a different HW setup than in the current FPGA Oberon design, where
the video RAM is physical part of the overall RAM of 1 MB and only covers
one bitmap.

-----Original Message-----
From: Oberon <oberon-bounces at lists.inf.ethz.ch> On Behalf Of Treutwein
Sent: Thursday, November 8, 2018 2:37 PM
To: 'ETH Oberon and related systems' <oberon at lists.inf.ethz.ch>
Subject: Re: [Oberon] Oberon 2 compiler for RISC5

> I wonder if 4 megs are enough. 

Ceres-1 had 2MB and Ceres-3 4MB, so it should be enough even for System 3
See the HW specs linked in https://en.wikipedia.org/wiki/Ceres_(workstation)

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