[Oberon] Re (2): BRAM
joerg.straube at iaeth.ch
Sat Feb 9 21:42:29 CET 2019
In the newest RISC-5 implementation the CPU‘s registers are stored in BRAM. See Registers.v
If in the future a cache will be implemented to enable DRAM (iso SRAM), this L1 cache might be implemented in BRAM as well.
Am 09.02.2019 um 21:30 schrieb <peter at easthope.ca> <peter at easthope.ca>:
>> Field-programmable gate arrays (FPGAs), ie chips full of uncommitted logic
>> building-blocks ...
> Yes, your explanation is very helpful. Thanks, ... L.
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