[Oberon] Re (2): BRAM

Skulski, Wojciech skulski at pas.rochester.edu
Sun Feb 10 03:37:44 CET 2019

Jörg Straube [joerg.straube at iaeth.ch] wrote:
Sent: Saturday, February 9, 2019 3:42 PM

> In the newest RISC-5 implementation the CPU‘s registers are stored in BRAM. See Registers.v
> If in the future a cache will be implemented to enable DRAM (iso SRAM), this L1 cache might be implemented in BRAM as well.

Registers.v dated 1.2.2018 use distributed memory for the register file. The instantiated "primitive" is RAM16X1D. The comment in the file says "//triple port register file, duplicated LUT array". LUT means "look up table" in Xilinx speak. These LUTs are the smallest 16 bit distributed blocks of RAM.

This design is interesting. It has one input and three outputs. It uses two parallel blocks of 16 LUTs, because each LUT can have two outputs. Two outputs come from the first LUT array of 16 registers. The third output comes from the second LUT array, whose 2nd output is left open. 

Using BRAM would be very wasteful because the BRAM is 18 kbits, while sixteen 32 bit registers need 16*32= 512 bits. In this case the distributed memory is much more appropriate.

The design with two LUT arrays uses 1024 bits. It could be shrank to 512 bits by overclocking, because the addresses could be muxed at twice the clock speed. It would complicate the design. Such optimization could be worth considering if one was using a very small FPGA with very limited logic resources.


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