lab.eas at gmail.com
Tue Feb 12 01:19:56 CET 2019
How is this possible ?!
In the final analysis an N bit RAM word must consist of N <adjacent>
bistables: each consisting of 2 transistors.
Apparently they make a dedicated CPU which simulates the <smartRAM>.
Like making a dedicated CPU which takes 2 64bit inputs and produces
the floatingPointProduct, and then calling it a floating point
multiplication INSTRUCTION of the <parent CPU>.
On 2/10/19, Walter Gallegos <walter at waltergallegos.com> wrote:
> Additional point,
> BRAMs in Xilinx are more than a simple RAM but true dual port RAMs. That
> meas, the silicon provide two ports with simultaneous read/write access
> to same physical memory; so, you can read/write an address while
> read/write another address.
> Also, ports could have different widths, can be writing in 8 bits while
> reading in 32 bits from the other port, your have a FIFO with 8 bit
> input 32 bits output for free.
> For RiscCore I adopt the same solution as Microblaze, one BRAM port for
> data and the other for code; so, code and data coexist into same
> physical memory without need big multiplexers, and a peripheral have a 8
> bit digital video input but reading as 24+8 bits (RGB+mask) from
> processor side.
> A powerfully block, as an old Xilinx paper say about BRAM : "be creative".
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
More information about the Oberon