[Oberon] Cache

Jörg joerg.straube at iaeth.ch
Fri Feb 15 19:34:03 CET 2019

For a LD/ST you need two cycles, with a L0 cache I could imagine this should be doable (in most cases) in one cycle...


Am 15.02.19, 19:25 schrieb "Oberon im Auftrag von Paul Reed" <oberon-bounces at lists.inf.ethz.ch im Auftrag von paulreed at paddedcell.com>:

    Hi Joerg,
    > Format 2   49%  memory instructions (LDR/STR)  (<-- cache would really be
    > great!!)
    I'm not sure what you mean, why would cache be great?  Wouldn't it slow
    things down to add another layer?
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