[Oberon] Cache

Skulski, Wojciech skulski at pas.rochester.edu
Fri Feb 15 20:17:14 CET 2019

Jörg [joerg.straube at iaeth.ch] wrote:
>For a LD/ST you need two cycles, with a L0 cache I could imagine this should be doable (in most cases) in one cycle...

In most cases. But filling the cache would introduce indeterminacy to the execution, which is not a great idea in embedded systems. 

Cache is a method to speed up the execution if one is using a DRAM memory which has all these refresh and other delays. Another (better?) way to gain speed could be a thorough timing optimization to make RISC5 run faster. Or perhaps deeper pipelining. Both these modifications, if doable, would improve execution speed in a deterministic way. 

Adding cache will become necessary if one wants to run RISC5 on a board with DRAM, like Arty for example. In such a case the emphasis would be on a large software system, like System-3, which needs lots of RAM. Real time latencies would then become a price to pay for running a graphically intense system. 

I would vote for two versions of RISC5. One w/o a cache and speed improved with timing optimization. The other one with cache for running with DRAM memories. Both should be instruction-compatible, if this is possible at all.


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