paulreed at paddedcell.com
Fri Feb 15 21:46:19 CET 2019
> ...the cache would introduce indeterminacy to the execution,
Right, which Prof. Wirth wished to avoid as a stated aim.
> Cache is a method to speed up the execution if one is using
> a DRAM memory
Right, a complicated thing to overcome an even worse (but cheap) thing.
But surely this all misses the point - two cycles are needed for a load
and store because these operations require both an instruction fetch and a
memory read/write in the same instruction, to/from the same memory. So
that's why it seems to me that putting a cache in the way would just slow
things down, not speed them up.
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