[Oberon] Resend: Re: Risc-5 Instructions statistics
chris at cfbsoftware.com
Sun Feb 17 05:04:04 CET 2019
Keep in mind that RISC5, for example, is more a general purpose microcontroller rather than a general purpose microprocessor. It is the flexibility of configurations of the peripheral interfaces (GPIO, SPI, I2C etc.) possible using FPGAs that make them so appealing. The associated hardware can be off-the shelf systems that are not particularly special.
I was alerted recently to the fact that ARM has made their Cortex-M3 architecture available as a softcore processor for Xilinx FPGA devices. I suspect they can see 'the writing is on the wall',
> -----Original Message-----
> From: Oberon [mailto:oberon-bounces at lists.inf.ethz.ch] On Behalf Of
> Walter Gallegos
> Sent: Sunday, 17 February 2019 12:57 PM
> To: oberon at lists.inf.ethz.ch
> Subject: Re: [Oberon] Resend: Re: Risc-5 Instructions statistics
> Hi Paul,
> In the general picture I agree, the evil is in the details.
> Implementing a general propose microprocessor system alone in FPGA is
> impractical beyond the research or ASIC prototypes. For industrial
> applications the microprocessor must coexist with some special
> hardware that justifies the use of FPGA. In this environment, wasting
> DSP blocks could be a not recommended technique.
> El 16/2/19 a las 14:36, Paul Reed escribi :
> > Hi Walter,
> >> Confirms experimental trends from my applications; example, has no
> >> sense waste DSP48 blocks implementing a 32 X 32 bits
> > Well it depends what you're doing! As I said, YMMV.
> > Configurable hardware, for the first time for a lot of us, gives us
> > the possibility to just go and do something in hardware, rather
> > endlessly try to optimise software to do it as fast as possible on
> > general-purpose architecture.
> > Cheers,
> > Paul
> > --
> > Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related
> > systems https://lists.inf.ethz.ch/mailman/listinfo/oberon
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