[Oberon] Resend: Re: Risc-5 Instructions statistics

Walter Gallegos waltergallegos at vera.com.uy
Sun Feb 17 03:26:57 CET 2019

Hi Paul,

In the general picture I agree, the evil is in the details.

Implementing a general propose microprocessor system alone in FPGA is 
impractical beyond the research or ASIC prototypes. For industrial 
applications the microprocessor must coexist with some special hardware 
that justifies the use of FPGA. In this environment, wasting DSP blocks 
could be a not recommended technique.



El 16/2/19 a las 14:36, Paul Reed escribió:
> Hi Walter,
>> Confirms experimental trends from my applications; example, has no sense
>> waste DSP48 blocks implementing a 32 X 32 bits multiplication.
> Well it depends what you're doing!  As I said, YMMV.
> Configurable hardware, for the first time for a lot of us, gives us the
> possibility to just go and do something in hardware, rather than endlessly
> try to optimise software to do it as fast as possible on a general-purpose
> architecture.
> Cheers,
> Paul
> --
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
> https://lists.inf.ethz.ch/mailman/listinfo/oberon

More information about the Oberon mailing list