[Oberon] What is the status of Lola-2 and its use in the FPGAversion ofProject Oberon?
paulreed at paddedcell.com
Fri Mar 15 09:58:23 CET 2019
> How do you decide whether to use
> Lola-2 or Verilog?
I prefer to use Lola wherever possible, it's clearer than either
(System)Verilog or VHDL. If a feature requires special features not
supported by Lola, I wrap it in Verilog. The main cause of this
currently is library identifiers (e.g. "_" characters), but in fact it's
really wrapping the nonportable pieces.
> Are there projects/project sizes where you would
> not recommend to use Lola-2?
Sorry, this is a rather general question on which I cannot give any
solid data. I have not compared projects with and without, in any
meaningful way. I am really talking only about personal preferences. I
suggest you could try it, and see if it works for you, that's all.
> Is it necessary to modify the generated
> Verilog code or can it directly be synthesized and placed/routed for
> an FPGA?
As Wirth describes, the Verilog generated by Lola-2 is used directly as
input to synthesis. Verilog is used as a kind of intermediate language
in order to get round the (often) proprietary nature of the FPGA
The original version of Lola compiled directly to a PAL fuse file or to
an early FPGA bitstream, see http://www.cs.inf.ethz.ch/lola/
Wirth ended up using Verilog to define the TRM and RISC5 rather than
VHDL, I think, because his colleagues Chuck Thacker and Ling Liu were
using Verilog. But I know he's not impressed by either language.
> ... it's not obvious what is
> synthesized and how.
This is indeed part of the insanity of FPGAs. Like having a compiler
which uses a different optimisation backend picked at random again and
again, for each function, for each compile. With the original Lola,
Wirth took a much more sensible approach (as always).
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