[Oberon] What is the status of Lola-2 and its use in the FPGAversion ofProject Oberon?

rochus.keller at bluewin.ch rochus.keller at bluewin.ch
Thu Mar 14 16:02:09 CET 2019

Dear Mr. Reed

Thank you very much for your response.

> I've used it in my own commercial work where it has had 
> some nice advantages.

Could you please elaborate on this? How do you decide whether to use Lola-2 or Verilog? Are there projects/project sizes where you would not recommend to use Lola-2? Is it necessary to modify the generated Verilog code or can it directly be synthesized and placed/routed for an FPGA?

> https://www.inf.ethz.ch/personal/wirth/news.txt

Thanks for the link. I didn't discover that yet. Very useful.

I had a look at different Verilog alternatives but think that a HDL embedded in another programming language essentially suffers from the same disadvantages like Verilog, i.e. it's not obvious what is synthesized and how. Lola-2 seems to have advantages in that regard, but I can't assess its limitations right now. Actually I'm trying to find out if it's worth developing a QtCreator plugin for it, analogous to https://github.com/rochus-keller/VerilogCreator.


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