[Oberon] What is the status of Lola-2 and its use in theFPGAversion ofProject Oberon?
paulreed at paddedcell.com
Fri Mar 15 13:53:52 CET 2019
>> I wrap it in Verilog
> How do you do that? By just using the Lola-2 to Verilog translated
> files in a Verilog project?
Yes. Sorry for being confusing, that's not the phrase I should have
used. If I have to code in Verilog, I keep it to a small (usually
nonportable) module and make sure the interface to that module is
definable in Lola (e.g., doesn't have any underscores). On another chip
the Verilog is different, but the interface and the Lola are the same.
> Is it really primarily a question of preference, or are there
> important features in Verilog (besides underscores in names) which are
> not available in Lola-2?
I haven't found any for what I need. But I'm not an expert on
(System)Verilog and don't intend to be. Ever.
> in a
> real-world FPGA project you usually have to use vendor provided
> modules or specific idioms in the Verilog code to achieve decent
> efficiency and performance.
And sometime not even then do you achieve efficiency and/or performance.
> a Lola-2 to bitstream compiler would again be
> feasible today by re-using the
> https://github.com/cliffordwolf/icestorm and
> https://github.com/SymbiFlow toolchains. Yosys could be modified to
> accept Lola-2 input or the Lola-2 compiler could be extended to
> generate RTLIL.
I know. I've experimented with doing some of that, in various ways.
Lola is pretty easy to play with.
As many people have pointed out, Project IceStorm is (also Projects
Trellis and X-Ray are) a real game-changer, where the game, as far as
I'm concerned, can't change soon enough.
> But of course this only makes sense if Lola-2 has
> enough expressiveness for a majority of real-world designs.
And not even then, because the Lola to Verilog to bitstream route works
fine as it is. It would presumably make sense only for some other
More information about the Oberon