[Oberon] What is the status of Lola-2 and its use intheFPGAversion ofProject Oberon?

rochus.keller at bluewin.ch rochus.keller at bluewin.ch
Fri Mar 15 14:17:28 CET 2019

Thanks again for your response and the clarifications.

> But I'm not an expert on (System)Verilog

Sorry, I should have more precisely asked "are there important features in the synthesizable subset of Verilog 05". I agree that SystemVerilog is a totally overengineered beast, but some parts are really useful, e.g. a subset of the assertions which even allow formal verification. That's something I personally would miss in Lola-2. Another thing would be Enums, but I'm aware that these are syntactic sugar and were left out in the tradition of Oberon.
But from your response I conclude that Lola-2 is sufficiently expressive for a majority of real-world designs with the exception of some vendor specific features, but these can be encapsulated into something (Verilog or whatever) with a Lola-2 compatible interface, so a Lola-2 developer would not have to bother with their implementation details. Plese correct me, if I misinterpreted you.

> I've experimented with doing some of that, in various ways.

Is this publicly available somewhere?

> And not even then, because the Lola to Verilog to bitstream 
> route works fine as it is.

True, but my point was that it makes little sense to use Lola-2 when the developer has to fall back to Verilog constantly because only a fraction of the design can be expressed in Lola-2 or for testing and simulation purpose. To be really useful Lola-2 should enable people to develop full FPGA or ASIC designs without being forced to also master the full Verilog/SystemVerilog trickery. Or do you think this is an unreasonable assumption?


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