[Oberon] Assumed issue in the Lola-2 compiler

Jörg Straube joerg.straube at iaeth.ch
Mon Apr 22 19:49:03 CEST 2019


> I also would like to discuss whether there is a way to avoid using a Xilinx specific module for TS() in the Verilog code generated by the Lola-2 compiler, see e.g.  https://github.com/rochus-keller/Lolac/blob/1cac988503e6b081619848a1fe11b96e106e9c04/Examples/RISC5_translated/RISC5Top.v#L49

In my point of view the Lola compiler could translate tri-state (0, 1, Z) buffers to more „standard“ Verilog.

Something like:

module tristate_buffer(I, enable, O);
  input I, enable;
  output O;
  assign O = enable ? I : 1'bz;

But I guess the IOBUF primitive will be much more optimized in terms of routing and timing.

If you have another FPGA board with another synthesizer tool, the easiest is probably to modify LSV to generate the optimized tri-state primitives for your board.


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