[Oberon] Oberon on ULX3S explanation
vordah at gmail.com
Wed Nov 13 08:59:36 CET 2019
I don't know how SDRAM in oberon works :)
Valentin took SDRAM driver for next186, equipped
it with some cache, I took valentin's work for his "ohm"
board and ported to my "ulx3s" because both boars
have practically identical hardware just a bit different wiring
On 11/13/19, Paul Reed <paulreed at paddedcell.com> wrote:
> Hi Lyall,
>> In my understanding, a typical PC uses DRAM. Kernel.Mod has several
>> CONSTs defined under (* memory management *). Is memory operation in
>> S3, Native Oberon, useful as an example?
> Sadly not, except in the very broadest sense. In a PC, the hardware is
> designed by the manufacturers and the software can use it because it
> conforms to a de-facto standard arrangement. We don't get to change it.
> With an FPGA board, we design the hardware ourselves - hopefully
> enabling an understanding of how things work at this level.
> Unfortunately, although commonly-used because it's cheap per bit,
> synchronous DRAM is much more complicated than the fast asynchronous
> static RAM used in the Oberon FPGA reference design. Getting a
> description of how this was implemented on the ULX3S board would have
> been useful in understanding the design trade-offs, but unfortunately
> all we got was another advert.
> Rowhammer (https://en.wikipedia.org/wiki/Row_hammer) is an example of a
> security exploit in PCs which takes advantage of the complexity of the
> PC's SDRAM implementation.
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
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