[Oberon] Oberon on ULX3S explanation
skulski at pas.rochester.edu
Wed Nov 13 16:22:27 CET 2019
> Unfortunately, although commonly-used because it's cheap per bit,
> synchronous DRAM is much more complicated than the fast asynchronous
> static RAM used in the Oberon FPGA reference design. Getting a
> description of how this was implemented on the ULX3S board would have
> been useful in understanding the design trade-offs, but unfortunately
> all we got was another advert.
There are some very good and well documented designs on OpenCores. Whether or not to use them and which one is another matter, but the documentation is worth pursuing. I do not endorse any of these designs because I have not used them. My recommendation concern the documents. Download, unpack, and read the documents before pursuing any given firmware. Or before designing any board, for that matter. In the past I was guilty of designing boards based on hardware specifications without first looking into firmware issues. Not anymore!
http://opencores.org/project,sdr_ctrl -- 8/16/32 bit SDRAM Controller; 28-page manual
http://opencores.org/project,hpdmc -- DDR DRAM targeting video
http://opencores.org/project,wbddr3 -- a horror story about DDR3
More information about the Oberon