[Oberon] Oberon on ULX3S explanation

D EMARD vordah at gmail.com
Thu Nov 14 06:47:51 CET 2019

I didn't go that deep but I use SDRAM for my 2D video acceleration
at another project f32c. SDRAM can display horizontal 20 sprites of
32 pixel width (32 byte each, full screen filled with sprites horizontally)
while DDR3 can do I think about 24 then they start to flicker

See, dynamic RAMs are actually kinda block devices similar to SD
cards, only "blocks" are different at SDRAM and DDR. Access times
for single cell are the same 70-80ns silicon tech limit, only block
sizes differ.
For DDR, you can address and read 1K bytes or 1 byte - it will take
the same time
For SDRAM the break-even is around 4-16 bytes depending on the driver.

On 11/14/19, Skulski, Wojciech <skulski at pas.rochester.edu> wrote:
>> when jumping often to random addresses and fetching small amount
>> of data each time, they have less latency and thus work are faster than
>> DDRx
> Could you provide some numbers concerning your board? How many nanoseconds
> have you seen per reading or writing 32-bit words from random SDRAM
> locations?
> Thank you,
> Wojtek
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