[Oberon] Oberon on ULX3S explanation

Skulski, Wojciech skulski at pas.rochester.edu
Thu Nov 14 16:47:43 CET 2019


>See, dynamic RAMs are actually kinda block devices similar to SD
>cards, only "blocks" are different at SDRAM and DDR. Access times
>for single cell are the same 70-80ns silicon tech limit, only block
>sizes differ. For DDR, you can address and read 1K bytes or 1 byte 
>- it will take the same time
> For SDRAM the break-even is around 4-16 bytes depending on the driver.

Thank you for the info. It would be good to know the actual random access time in a practical system using SDRAM. The numbers which we get from the chip data sheets are not necessarily realized in practice. If you could somehow gather this info then we would have at least one data point. 

Thank you,

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