[Oberon] Oberon on ULX3S explanation
joerg.straube at iaeth.ch
Thu Nov 14 22:07:04 CET 2019
Current VID.v shifts our pixel per pixel at pixelclk. It fetches a word when shift buffer is empty. So you need to be fast to have the next word ready in time...
But of course SDRAM is fast enough for the video. You just have to redesign VID.v so it caches a complete horizontal line during horizontal refresh.
> Am 14.11.2019 um 21:58 schrieb D EMARD <vordah at gmail.com>:
> Well it is known from other projects like minimig - amiga emulator
> for example, SDRAM access time is fast enough for the sprites,
> DDR3 is not, amiga will boot but sprites won't work
>> On 11/14/19, Skulski, Wojciech <skulski at pas.rochester.edu> wrote:
>> D EMARD:
>>> See, dynamic RAMs are actually kinda block devices similar to SD
>>> cards, only "blocks" are different at SDRAM and DDR. Access times
>>> for single cell are the same 70-80ns silicon tech limit, only block
>>> sizes differ. For DDR, you can address and read 1K bytes or 1 byte
>>> - it will take the same time
>>> For SDRAM the break-even is around 4-16 bytes depending on the driver.
>> Thank you for the info. It would be good to know the actual random access
>> time in a practical system using SDRAM. The numbers which we get from the
>> chip data sheets are not necessarily realized in practice. If you could
>> somehow gather this info then we would have at least one data point.
>> Thank you,
>> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
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