[Oberon] Re: Oberon on ULX3S explanation

peter at easthope.ca peter at easthope.ca
Fri Nov 15 19:52:07 CET 2019


According to Wikipedia, chips up to 2 MB are available for 
asynchronous and synchronous uses.
Therefore a board with 4 or 8 MB should be quite feasible.
From:	"Skulski, Wojciech" <skulski at pas.rochester.edu>
Date:	Thu, 14 Nov 2019 15:47:43 +0000
> It would be good to know the actual random access time in a 
> practical system using SDRAM. The numbers which we get from the chip 
> data sheets are not necessarily realized in practice. If you could 
> somehow gather this info then we would have at least one data point. 

This and other messages suggest, to me as naive reader, that you are 
reluctant to commit to SRAM on your RiskFive; still considering SDRAM.
Therefore I wonder whether cost is a concern.  But RiskFive is a 
high-end board.  Therefore unless the cost is extreme, it should be 
tolerable for RiskFive.

Regards,                                   ... Lyall E.

Tel: +1 604 670 0140            Bcc: peter at easthope. ca

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