[Oberon] SDRAM performance
vordah at gmail.com
Fri Nov 15 22:30:13 CET 2019
OK I see you considered all the hardware and the clocking issues
and it seems that you know the stuff :)
ok great, DDR and 166 MHz is within the easy reach and all FPGA have them.
well pushing some firmware should not be a big deal, I would store it
on SPI config flash for FPGA at address above the bitstream e.g. 0x200000
when bitstream starts it will take control over SPI flash, a single read command
with 3-byte address and SPI flash chip will stream bytes constantly then.
On 11/15/19, Skulski, Wojciech <skulski at pas.rochester.edu> wrote:
>>it would need additional time critical part: clock domain crossing
>>logic operating between 333 MHz RAM and say 50 MHz CPU/video.
>>FIFO of course. BTW, HyperRAM operates at up 166 MHz DDR, rather than 333
> Note that this was already implemented in the controllers which I referenced
> in my e-mail.
>>In our flagship digitizer we are receiving ADC data at 800 MHz. We also
>> interfaced the GbE PHY using the SGMII running at 1.25 GHz. It was not a
>> lottery. It was a careful design. But it was also lots of work. There is
>> no doubt here.
> I should have said "gigabits per second" rather than GHz. I often make this
> kind of mistake. The gigahertz are half of the gigabits. Sorry for that
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
More information about the Oberon