[Oberon] FPGA RISC byte access

Paul Reed paulreed at paddedcell.com
Thu Dec 19 16:02:16 CET 2019

Hi Wojtek,

>     trying to [understand the hardware description] I am now puzzled 
> with the
> individual byte access logic in RISC5 and RISC5top

See also "5.3. Implementing byte-access (RISC-3)" in "The Design of a 
RISC Architecture
and its Implementation with an FPGA":



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