[Oberon] FPGA RISC byte access
skulski at pas.rochester.edu
Thu Dec 19 17:07:19 CET 2019
thank you for the pointer! Yes, I did look at RISC.pdf before sending the e-mail. Section 3.5 says the following, quoted verbatim:
"The only addition to the processor interface is the signal ben (byte enable) derived from the modifier bit v in memory instructions."
The words "active high" are missing here too. "Derived from" can mean anything. Also, in the RISC5 ben was derived from p an q, not from v. So it is less than clear how this paper refers to RISC5.
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