[Oberon] FPGA RISC byte access

Skulski, Wojciech skulski at pas.rochester.edu
Fri Dec 20 14:41:11 CET 2019


> You’re right. Would be nice [to have a data sheet -- WS]. Please remember: NWs RISC5 is not the Chip itself but the microcode defining the chip/instruction set.

Functionally it is a chip. Fact that it is soft does not change its functionality. It is as real as an ASIC would have been, if someone is not changing its Verilog.

>The exact timings are defined by the FPGA used and the FPGA routing SW when it positions the logic elements in the FPGA.

Exact yes. Nominal no.

> As meanwhile the RISC5 microcode was implemented on different FPGAs, you would have to measure the signal timings yourself for your FPGA.

Yes for exact, no for nominal. By "nominal" I mean the sequence of signals issued by the RISC5 chip relative to clock. For example, the chip is issuing a read strobe "rd". Then it expects to receive the data from memory. Nominal specs are saying "in the same clock cycle", "next clock cycle", "two clocks later", etc. 

Every chip vendor provides this kind of info, usually in a form of a diagram. Take any data sheet for any memory chip (for example) and you will see such diagrams. They are needed to write the interface code.

The PO documents describe the history of development in detail, as well as the design decisions. But the product itself is undocumented. As a designer of the interface logic I would like to know inputs, outputs, their polarity, and the nominal sequencing of the in/out wires in terms of clock cycles. This information is missing. It would be good to know in order to use this chip in other designs.


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