[Oberon] FPGA RISC byte access
joerg.straube at iaeth.ch
Fri Dec 20 09:25:52 CET 2019
You’re right. Would be nice. Please remember: NWs RISC5 is not the Chip itself but the microcode defining the chip/instruction set.
The exact timings are defined by the FPGA used and the FPGA routing SW when it positions the logic elements in the FPGA.
As meanwhile the RISC5 microcode was implemented on different FPGAs, you would have to measure the signal timings yourself for your FPGA.
> Am 20.12.2019 um 05:51 schrieb Skulski, Wojciech <skulski at pas.rochester.edu>:
> thank you!
> RISC5, being a chip, would benefit from a data sheet. We worked for quite a while on interfacing RISC5 to the ZBT memory. This task would have been much easier if we knew the signal waveforms. I mean, what is the time relation between the strobes, addresses, and data, plotted against the clock. I know that setup and hold times will depend on the FPGA technology, so these may be hard to specify. But the basic time structure is determined by the RISC5 design. All chip vendors provide this kind of information for all their products.
> The fact that even the polarities were not mentioned is just the tip of the iceberg. It is difficult to interface RISC5 with other components without knowing when the CPU is issuing the signals. Writing firmware without having this information is unnecessarily tough indeed.
> Thanks you again,
> From: Oberon [oberon-bounces at lists.inf.ethz.ch] on behalf of Joerg [joerg.straube at iaeth.ch]
> Sent: Thursday, December 19, 2019 12:10 PM
> To: oberon at lists.inf.ethz.ch
> Subject: Re: [Oberon] FPGA RISC byte access
> assign ben = p & ~q & v & ~stallX & ~stallL1; // byte enable
> If you look at above statement, this boils down to "ben = v".
> But "byte enable" is only valid for memory instructions (format F2: p=1,
> q=0) and the memory is not used by video (=stallX) and is in the correct
> cycle of LDR/STR (stallL1)
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
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