[Oberon] FPGA RISC memory interfacing
paulreed at paddedcell.com
Sun Dec 22 14:56:47 CET 2019
> I want to connect ... to a memory chip ... IS61NLP102418B-200B3L.
> ... A quick look at the RISC5 code reveals that the state machines seem
> not be present in this code...So this design is quite interesting.
> Most of the RISC5 code is combinational...
Right, it's not a pipelined design.
Also I think the intention is to explain its operation for a general
audience, not for an electronics designer. Nevertheless it's pretty
clear, certainly in comparison with most other designs out there.
To see the effects of the combinational choice, you would need to do
some more realistic simulation, e.g. post-synthesis, rather than just
simulating the Verilog source, to see the effects of the actual delays
in the real hardware, which are very significant.
That ISSI synchronous memory chip would probably work better with a
pipelined design like RISC-V. Prof. Wirth's RISC works well with
asynchronous SRAM, as has already been discussed.
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