[Oberon] QEMU target implementation for Oberon RISC architecture
oberon at x.colbyrussell.com
Tue Dec 31 17:11:15 CET 2019
On 12/30/19 9:11 AM, Charles Perkins wrote:
> Sometimes I am too clever for my own good. I thought I saw a way out
> of the name confusion. I'll make it clear that RISC5 is the correct
> name for the architecture.
In my personal notes, I've sometimes referred to it as RISC-W.
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