[Oberon] QEMU target implementation for Oberon RISC architecture

Jörg joerg.straube at iaeth.ch
Tue Dec 31 15:16:47 CET 2019


A remark on interrupts in ProjectOberon:
The current implementation of interrupts looks to me a little bit like a quick and dirty hack or proof of concept. I don‘t find it user-friendly a programmer has to import SYSTEM and has to know the „magic“ address 4. Let me explain.

Offering interrupts to the programmer needs three parts:
- CPU support: instructions to enable/disable interrupts and return from interrupts.
- Compiler support: PROCEDURE* is parsed and correct instructions are generated.
- OS support: an easy to use API to use the interrupt in a program.

Of course I can provide an API myself. Eg:

MODULE Interrupt; (* jr/31dec19 *)

  PROCEDURE* Empty; END Empty;

  PROCEDURE Install*(handler: PROCEDURE); (* handler=NIL: deactivate interrupts *)
    VAR instr: INTEGER;
      Kernel.Install(SYSTEM.ADR(Empty), 4);
      SYSTEM.GET(SYSTEM.VAL, INTEGER, handler)+4, instr);
      IF instr = 0A0E00000H THEN (* valid interrupt handler *)
        Kernel.Install(SYSTEM.VAL(INTEGER, handler), 4);
    END Install;

BEGIN Install(NIL) END Interrupt.

For me something like the above should be part of the inner core (e.g. Kernel.Mod) or at least a module of the outer core to be provided with the standard distribution.
With the above API, interrupts are easily consumable (no import of SYSTEM, all the nitty gritty details hidden in Interrupt.Mod)

IMPORT Interrupt;
VAR led, cnt: INTEGER;
PROCEDURE* Int; (*interrupt handler called every millisecond*)
    INC(cnt); IF cnt = 500 THEN led := 3 - led; LED(led); cnt := 0 END
  END Int;
PROCEDURE On*;  BEGIN Interrupt.Install(Int) END On;
PROCEDURE Off*;  BEGIN Interrupt.Install(NIL) END Off;
  led := 1; cnt := 0
END TestInt.


> Am 30.12.2019 um 16:12 schrieb Charles Perkins <chuck at kuracali.com>:
> Hi Paul and Jörg,
> Sometimes I am too clever for my own good. I thought I saw a way out of the name confusion. I'll make it clear that RISC5 is the correct name for the architecture. Also, I missed the CPU version bits in the emulator -- I will have to make sure the SYSTEM.H code works too... after I correct DIV for negative operands and finish floating point!  
> Of course this is just another emulator and the Oberon community already has plenty of those but I wanted to work with just one emulation platform across several porting efforts, and QEMU is to me the obvious choice. And as a side benefit it seems quite fast, comparatively. 
> Cheers,
> Chuck
>> On Mon, Dec 30, 2019 at 1:43 AM Jörg <joerg.straube at iaeth.ch> wrote:
>> Hi
>> You can ask the RISC processor to reveal its version with this code
>>    cpu := SYSTEM.H(2019) MOD 80H;
>>    IF cpu = 53H THEN       (* RISC5: with interrupts + floating-point, 31.8.2018 *)
>>    ELSIF cpu = 54H THEN (* RISC5a: no interrupts, no floating-point, 1.9.2018*)
>>    ELSIF cpu = A0H THEN (* RISC0, 26.12.2013 *)
>>    END;
>> br
>> Jörg
>> Am 30.12.19, 09:56 schrieb "Oberon im Auftrag von Paul Reed" <oberon-bounces at lists.inf.ethz.ch im Auftrag von paulreed at paddedcell.com>:
>>     Hi Chuck,
>>     > ...the target is named risc6
>>     > to avoid confusion with the already existing riscv target in qemu and
>>     > because in one communication (An Update of the RISC5 Implementation
>>     > [1]) Professor Wirth defines module RISC6 to introduce interrupts into
>>     > the architecture.
>>     Sorry I think that's a mis-print since it's the only occurrence, I'm 
>>     pretty sure the intention was to keep it as RISC5.  Apologies for any 
>>     confusion.
>>     As it happens most of the stuff for interrupts was there originally 
>>     anyway before the update, especially in the compiler.  The RISC5 source 
>>     on Prof. Wirth's site definitely contains the interrupt code now.  
>>     There's also a RISC5a version, without interrupts and without 
>>     floating-point.
>>     Cheers,
>>     Paul
>>     --
>>     Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
>>     https://lists.inf.ethz.ch/mailman/listinfo/oberon
>> --
>> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
>> https://lists.inf.ethz.ch/mailman/listinfo/oberon
> --
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
> https://lists.inf.ethz.ch/mailman/listinfo/oberon
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.inf.ethz.ch/pipermail/oberon/attachments/20191231/0461c82c/attachment.html>

More information about the Oberon mailing list