[Oberon] Unlimited Oberon System for any board
skulski at pas.rochester.edu
Mon May 4 04:06:48 CEST 2020
thank you for the clarifications.
> That is an ambitious project - I wish you every success with it.
Well, what I outlined was not a project but rather a roadmap inspired by Joerg's remarks on drivers.Let me restate. The present NW/PR System filled the then available board to almost 100%. That system could not be much different because otherwise it would not fit. This being the case, there is not much need for Joerg's driver framework because there will not be much to drive with the old Digilent board. It is almost 100% full.
So I tried to say "what is next" such that the System can grow. I recalled the history in order to better outline the sources of the limitations. My conclusions were:
a) Since the newer boards use more capable FPGAs, the SoC itself can grow. (Examples, which I am adding now: the LX9 on the Pepino would be 60% full. If Pepino was assembled with LX25, then it would be 22% full.)
b) RAM was the next limitation inherited from the original design. We all probably agree that running the OS in 1 MB was very admirable, but there is no room to grow. Increasing the RAM to 2 MB is nice, but it still does not allow for substantial software.
c) Then I said that adding more RAM would allow substantial new developments. Otherwise we are still trying to cram little projects into little RAM, with little overall impact.
The rest of my post was trying to discuss the ramifications. It was not a description of any project. A project can maybe appear in the future.
> I consider 10 years to be 'a long time' for the target audience of this sort of product.
I stand corrected. Yes, it is a good period of time. The board can still be purchased on eBay. Unfortunately, Digilent does not release the design files for their "retired" boards. From this perspective it is a dead end. See https://store.digilentinc.com/spartan-3-board-retired/
>> Pepino could be assembled with 2 MB, but I am not sure if it was.
>I can confirm it was. I purchased a 2 MB Pepino from Saanlima in Jan 2016.
Good! But this does not support substantial developments which some can have on their minds. Like for example porting System 3 to RISC5. Note that I am not asking whether it makes sense. I am only pointing out that it is impossible.
The bottom line: Our ability to pull off anything substantial with RISC5 is limited by available RAM. We can try emulators with more RAM, but we cannot then run these developments on a real board with real RISC5.
> Note that there was a significant change to the RISC5 implementation in Verilog in 2018.
Sure I know. Both Pepino and RiskFive will have no problem with such changes thanks to larger FPGAs. At the same time, both boards are limited to either 2 MB or 4 MB, which is not a lot if one considers a substantial software project for the real RISC5.
> There is (now) no such 1 MB barrier. See above.
A 2 MB barrier or 4 MB barrier is still a barrier. Consider System-3. I am not a big fan of S3, but I do not like the situation that it cannot be approached due to lack of RAM.
>> 8. The RISC5c can be then used with commercial FPGA boards which tend to use
>> the DDR chips these days.
>That would be useful. I thought that has already been done by the Radiona guys, hasn't it?
AFAIK it has not made it into the mainstream Oberon System yet. It would be good if it did. Our mainstream is still the static RAM up to 2 MB, or up to 4 MB if you admit RiskFive. Lack of RAM can be a serious limitation.
We need both the frugal firmware for embedded projects like Astrobe, and the DDR-capable firmware for those substantial projects which could materialize if more RAM could be tackled with RISC5.
My current projects will probably fit into 4 MB, until I have some more crazy ideas one day. But being able to show off System 3 running on the FPGA board would be nice. This would require DRAM, I think.
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