[Oberon] [EXT] Re: Project Oberon, RISC-V Edition

Skulski, Wojciech skulski at pas.rochester.edu
Mon Dec 7 06:06:21 CET 2020


> FYI you can also use the Arty A7-100 board to run the official Project Oberon Workstation using entirely off-the-shelf parts i.e. Digilent's VGA, SDCard and PS/2 PMOD boards and cables. I succeeded in implementing this recently using only the BRAM that is on the Artix-7 100T board running at a clock speed 50% higher than normal (i.e. 37.5 MHz). As this means that the total RAM available is only 512 KB (instead of the usual 1 MB) this does present some challenges. However, it is possible to use the system to compile itself, using all of the standard Project Oberon modules from Prof Wirth's site, even with the limited memory that is available.

This is wonderful.

I also think that it would pay off to ask some good FPGA programmer (not me, I am not a good one) to interface the DDR3 memory to RISC5 SoC. The interface is in fact available from Open Arty SoC by Dan Gisselquist. You can find him on OpenCores. He is also running a dedicated website. It is a matter of pulling off the DDR3 controller for Arty and then interfacing it to the rest of the system like Joerg and Magnus did for Pipistrello.

The downside is that the DDR3 controller is taking lots of FPGA resources which RISC-V also needs. So maybe Genesys 2 would be a better solution for truly ambitious designs. Its Kintex-7 is quite hefty.


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