[Barrelfish-users] Barrelfish for custom tile-based architecture

Bjørn Christian Seime bcseime at gmail.com
Mon Aug 26 18:17:09 CEST 2013


We are two Master students from NTNU (Norwegian University of Science and Technology) currently working on a project in which we are to implement a minimal operating system for a simple, experimental architecture[1], preferably by porting Barrelfish. The architecture consists of multiple Amber[2] cores connected in a tile-based architecture. These cores are fairly simple; specifically, they do not have an MMU, or any other hardware mechanisms available for implementing virtual memory or memory protection. The amount of memory is also fairly limited (around 32MB), and there is no hard drive available either to use as backing storage. 

In many ways, the architecture seems like a good fit for the multikernel approach used in Barrelfish. However, as (to our knowledge) all the existing ports of Barrelfish have virtual memory support, we are worried as to whether some part of the operating system is relying on its existence. We have read some previous theses on porting Barrelfish to new architectures[3,4,5]; all of them consider the challenges of implementing virtual memory, but none discuss the reliance on it of other parts of the system. As this is something we might not discover until a late stage in the porting process, we figured that consulting the experts who might immediately know of problems we would encounter would be a pragmatic approach. Can you think of any issues which would prohibit porting Barrelfish to this MMU-less environment?

Bjorn C. Seime and Benjamin Bjornseth

[1]: http://research.idi.ntnu.no/eecs/shmac
[2]: http://en.wikipedia.org/wiki/Amber_(processor_core)
[3]: http://www.diva-portal.org/smash/get/diva2:635212/FULLTEXT01.pdf
[4]: www.barrelfish.org/scheidegger-bachelor-netronome.pdf‎
[5]: www.barrelfish.org/hitz-bachelor-multicore-arm.pdf‎

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