[Oberon] Oberon ->(Chisel?) -> Verilog

greim greim at schleibinger.com
Thu Dec 26 16:03:43 CET 2013

Hi ,

i am very surprised and impressed about the "Oberon 2013 edition" project.
The future is embedded as you may see for example at all the hype around 
Arduinio and RasperryPi and of course all SmartPhone Aps.

The problem is that all this embedded devices around are programmed 
mostly by "stupid" electronic engineers (like me for more then 30 years) 
and that the information sciences are focused on the big irons (also a 
modern PC is a big iron) for decades.

Its a fantastic decision of Professor Wirth to use a FPGA instead of any 
ARM or similar 32bit device!

The only ugly spot or missing link in this project is the Verilog 
language, but i know that VHDL and Verilog are the only real world tools 
for this job..
BUT i like to make a hint to the Chisel project 
(http://www.inf.ethz.ch/personal/wirth/ProjectOberon/index.html) .

They expanded SCALA (an up-polished JAVA) as a front-end for Verilog.
 From the CHISEL/Scala code they are generating Verilog and C++ code for 
the simulation.

So porting/making a kind of Chisel to Oberon would be the missing link 
in the whole project.
So anybody out there knowing both language good enough?
Is there any chance to do this?


Markus Greim

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